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Advisor(s)
Abstract(s)
In recent years, there has been a rapid increase in the use of microprocessor-based systems in critical areas where failures imply risks to human lives, the environment or expensive equipment. One solution for avoiding a possible disaster lays in the use of dependable systems, able to tolerate and eventually correct faults, requiring high quality validation & verification in their development cycle. The PhD thesis here described aims to contribute a methodology that reuses a proposed standard debug & test infrastructure (NEXUS 5001) to access the microprocessor core with the objective of supporting the validation and verification steps of the fault- tolerant mechanisms through fault injection campaigns. For the purpose of later demonstrating the proposed methodology, a target microprocessor available as a synthesisable core for programmable components will be used. This aspect is crucial because it allows us to implement a prototype for demonstration purposes on a reconfigurable device. From these elements a fault injection infrastructure that can be utilized not only for validating the fault- tolerant characteristics of microprocessors but also for debugging and data collecting operations will be developed.
Description
Keywords
Boundary scan Fault injection Dependability