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Bus-Contention Aware WCRT Analysis for the 3-Phase Task Model Considering a Work- Conserving Bus Arbitration Scheme

2021-12-14Journal article Open access
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dc.contributor.authorArora, Jatin
dc.contributor.authorMaia, Cláudio
dc.contributor.authorRashid, Syed Aftab
dc.contributor.authorNelissen, Geoffrey
dc.contributor.authorTovar, Eduardo
dc.date.accessioned2022-10-03T15:35:41Z
dc.date.available2022-10-03T15:35:41Z
dc.date.issued2021-12-14
dc.description.abstractToday multicore processors are used in most modern systems that require computational logic. However, their applicability in systems with stringent timing requirements is still an ongoing research. This is due to the difficulty of ensuring the timing correctness of tasks executing on a multicore platform that comprises a number of shared hardware resources, e.g., caches, memory bus and the main memory. Concurrent accesses to any of these shared resources can generate uncontrolled interference, which complicates the estimations of tasks' worst-case execution time (WCET) and the worst-case response time (WCRT). The use of the 3-phase task execution model helps in upper bounding the contention due to the sharing of bus/main memory in multicore systems. It divides the execution of tasks into distinct memory and execution phases, where tasks can only access the bus/main memory during their memory phases. This makes bus/memory access patterns of tasks more predictable, enabling a preciser computation of bus/memory contention. In this work, we show how the bus contention can be computed for the 3-phase task model considering a work-conserving, i.e., round-robin (RR) based, arbitration policy at the memory bus. This is different from existing works that analyze the time-division multiple access (TDMA) and first-come-first-serve (FCFS) based bus arbitration policies. First, we present a solution to model the bus contention that can be suffered/caused by tasks executing on the same/remote cores of a multicore system under an RR-based bus arbitration scheme. We then evaluate the impact of resulting bus contention on taskset schedulability. Experimental results show that our proposed RR-based bus contention analysis can improve taskset schedulability by up to 100 percentage points than the TDMA-based analysis and up to 40 percentage points than the FCFS-based bus contention analysis.pt_PT
dc.description.sponsorshipThis work was partially supported by National Funds through FCT/MCTES (Portuguese Foundation for Science and Technology), within the CISTER Research Unit (UIDB-UIDP/04234/2020); also by the Operational Competitiveness Programme and Internationalization (COMPETE 2020) under the PT2020 Partnership Agreement, through the European Regional Development Fund (ERDF), and by national funds through the FCT, within project POCI-01-0145-FEDER-029119 (PREFECT); also by the European Union’s Horizon 2020 - The EU Framework Programme for Research and Innovation 2014-2020, under grant agreement No. 732505. Project “TEC4Growth - Pervasive Intelligence, Enhancers and Proofs of Concept with Industrial Impact/NORTE-01-0145-FEDER000020” financed by the North Portugal Regional Operational Programme (NORTE 2020), under the PORTUGAL 2020 Partnership Agreement; also by FCT, under PhD grant 2020.09532.BD.pt_PT
dc.description.versioninfo:eu-repo/semantics/publishedVersionpt_PT
dc.identifier.doi10.1016/j.sysarc.2021.102345pt_PT
dc.identifier.urihttp://hdl.handle.net/10400.22/20906
dc.language.isoengpt_PT
dc.publisherElsevierpt_PT
dc.relationUIDB-UIDP/04234/2020pt_PT
dc.relationPOCI-01-0145-FEDER-029119pt_PT
dc.relationLightweight Computation for Networks at the Edge
dc.relationBus-Aware Schedulability Analysis in Multiprocessor Real-Time Systems
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/4.0/pt_PT
dc.subjectReal-Time Systemspt_PT
dc.subjectMulticore Processorspt_PT
dc.subjectPartitioned Schedulingpt_PT
dc.subjectPhased Execution Modelpt_PT
dc.subjectBus Contentionpt_PT
dc.subjectSchedulability Analysispt_PT
dc.titleBus-Contention Aware WCRT Analysis for the 3-Phase Task Model Considering a Work- Conserving Bus Arbitration Schemept_PT
dc.title.alternative211004pt_PT
dc.typejournal article
dspace.entity.typePublication
oaire.awardTitleLightweight Computation for Networks at the Edge
oaire.awardTitleBus-Aware Schedulability Analysis in Multiprocessor Real-Time Systems
oaire.awardURIinfo:eu-repo/grantAgreement/EC/H2020/732505/EU
oaire.awardURIinfo:eu-repo/grantAgreement/FCT/POR_NORTE/2020.09532.BD/PT
oaire.citation.titleJournal of Systems Architecturept_PT
oaire.citation.volume122pt_PT
oaire.fundingStreamH2020
oaire.fundingStreamPOR_NORTE
person.familyNameArora
person.familyNameMaia
person.familyNameTovar
person.givenNameJatin
person.givenNameCláudio Roberto Ribeiro
person.givenNameEduardo
person.identifier.ciencia-id8816-61C3-8763
person.identifier.ciencia-idEC13-23BF-2018
person.identifier.ciencia-id6017-8881-11E8
person.identifier.orcid0000-0001-6198-6852
person.identifier.orcid0000-0002-6567-4271
person.identifier.orcid0000-0001-8979-3876
person.identifier.scopus-author-id7006312557
project.funder.identifierhttp://doi.org/10.13039/501100008530
project.funder.identifierhttp://doi.org/10.13039/501100001871
project.funder.nameEuropean Commission
project.funder.nameFundação para a Ciência e a Tecnologia
rcaap.rightsopenAccesspt_PT
rcaap.typearticlept_PT
relation.isAuthorOfPublication21bbedd3-1ba1-40a2-9ceb-42bbfd0abbee
relation.isAuthorOfPublication382626bf-f6e8-427b-b5fa-e470b5b0fb03
relation.isAuthorOfPublication80b63d8a-2e6d-484e-af3c-55849d0cb65e
relation.isAuthorOfPublication.latestForDiscovery21bbedd3-1ba1-40a2-9ceb-42bbfd0abbee
relation.isProjectOfPublication53ade512-30d8-4f8c-a0a4-9e38aee21e55
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