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Improved Bus Contention Analysis for 3-Phase Tasks

dc.contributor.authorArora, Jatin
dc.contributor.authorRashid, Syed Aftab
dc.contributor.authorNelissen, Geoffrey
dc.contributor.authorMaia, Cláudio
dc.contributor.authorTovar, Eduardo
dc.date.accessioned2023-07-05T14:51:05Z
dc.date.available2023-07-05T14:51:05Z
dc.date.issued2023-05-30
dc.description.abstractThe 3-phase task execution model has shown to be a good candidate to tackle the memory bus contention problem. It divides the execution of tasks into computation and memory phases that enable a fine-grained memory bus contention analysis. However, existing works that focus on the bus contention analysis for 3-phase tasks, neglect the fact that memory bus contention strongly relates to the number of bus/memory requests generated by tasks, which, in turn, depends on the content of the cache memories during the execution of those tasks. These existing works assume that the worst-case number of bus/memory requests will be generated during all the memory phases of all tasks, irrespective of the already existing content in the cache memory. This overestimates the memory bus contention of tasks, leading to pessimistic worst-case response time (WCRT) bounds. This work proposes a holistic approach towards bus contention analysis for 3-phase tasks by (1) deriving an upper bound on the actual cache misses of tasks that lead to bus/memory requests; (2) improving State-of-the-Art (SoA) bus contention analysis of two bus arbitration schemes that dominate all existing works on the bus contention analysis for 3-phase tasks; and (3) performing an extensive experimental evaluation under different settings to compare the proposed analysis against the SoA. Results show that incorporating a tighter bound on the number of cache misses of tasks into the bus contention analysis can lead to a significant improvement in task set schedulability.pt_PT
dc.description.sponsorshipThis work was supported by the CISTER Research Unit (UIDP/UIDB/04234/2020), financed by National Funds through FCT/MCTES (Portuguese Foundation for Science and Technology); by project ADACORSA (ECSEL/0010/2019 - JU grant nr. 876019) financed through National Funds from FCT and European funds through the EU ECSEL JU. The JU receives support from the European Union’s Horizon 2020 research and innovation programme and Austria, Sweden, Spain, Italy, France, Portugal, Ireland, Finland, Slovenia, Poland, Netherlands, Turkey - Disclaimer: This document reflects only the author’s view and the Commission is not responsible for any use that may be made of the information it contains. This work is also a result of the work developed under project Aero.Next Portugal (nº C645727867- 00000066) and FLY-PT (grant nº 46079, POCI-01-0247-FEDER-046079), also funded by FCT under PhD grant 2020.09532.BD.pt_PT
dc.description.versioninfo:eu-repo/semantics/publishedVersionpt_PT
dc.identifier.urihttp://hdl.handle.net/10400.22/23192
dc.language.isoengpt_PT
dc.relationUIDP/UIDB/04234/2020pt_PT
dc.relationAirborne data collection on resilient system architectures
dc.relationAirborne data collection on resilient system architectures
dc.relationgrant nº 46079, POCI-01-0247-FEDER-046079pt_PT
dc.relationBus-Aware Schedulability Analysis in Multiprocessor Real-Time Systems
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/4.0/pt_PT
dc.subject3-phase task executionpt_PT
dc.subjectMemory bus contentionpt_PT
dc.titleImproved Bus Contention Analysis for 3-Phase Taskspt_PT
dc.title.alternative230505pt_PT
dc.typejournal article
dspace.entity.typePublication
oaire.awardTitleAirborne data collection on resilient system architectures
oaire.awardTitleAirborne data collection on resilient system architectures
oaire.awardTitleBus-Aware Schedulability Analysis in Multiprocessor Real-Time Systems
oaire.awardURIinfo:eu-repo/grantAgreement/FCT/3599-PPCDT/ECSEL%2F0010%2F2019/PT
oaire.awardURIinfo:eu-repo/grantAgreement/EC/H2020/876019/EU
oaire.awardURIinfo:eu-repo/grantAgreement/FCT/POR_NORTE/2020.09532.BD/PT
oaire.citation.conferencePlaceNiigata, Japan, 30, Aug to 1, Sep, 2023,pt_PT
oaire.citation.title29th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2023). Technical Session. TOKI MESSE, .The paper is accepted as a full paper in RTCSA 2023.pt_PT
oaire.fundingStream3599-PPCDT
oaire.fundingStreamH2020
oaire.fundingStreamPOR_NORTE
person.familyNameArora
person.familyNameMaia
person.familyNameTovar
person.givenNameJatin
person.givenNameCláudio Roberto Ribeiro
person.givenNameEduardo
person.identifier.ciencia-id8816-61C3-8763
person.identifier.ciencia-idEC13-23BF-2018
person.identifier.ciencia-id6017-8881-11E8
person.identifier.orcid0000-0001-6198-6852
person.identifier.orcid0000-0002-6567-4271
person.identifier.orcid0000-0001-8979-3876
person.identifier.scopus-author-id7006312557
project.funder.identifierhttp://doi.org/10.13039/501100001871
project.funder.identifierhttp://doi.org/10.13039/501100008530
project.funder.identifierhttp://doi.org/10.13039/501100001871
project.funder.nameFundação para a Ciência e a Tecnologia
project.funder.nameEuropean Commission
project.funder.nameFundação para a Ciência e a Tecnologia
rcaap.rightsopenAccesspt_PT
rcaap.typearticlept_PT
relation.isAuthorOfPublication21bbedd3-1ba1-40a2-9ceb-42bbfd0abbee
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relation.isAuthorOfPublication.latestForDiscovery21bbedd3-1ba1-40a2-9ceb-42bbfd0abbee
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