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Cache Persistence-Aware Memory Bus Contention Analysis for Multicore Systems

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dc.contributor.authorAftab Rashid, Syed
dc.contributor.authorNelissen, Geoffrey
dc.contributor.authorTovar, Eduardo
dc.date.accessioned2020-10-21T11:30:48Z
dc.date.embargo2120
dc.date.issued2020
dc.description.abstractMemory bus contention strongly relates to the number of main memory requests generated by tasks running on different cores of a multicore platform, which, in turn, depends on the content of the cache memories during the execution of those tasks. Recent works have shown that due to cache persistence the memory access demand of multiple jobs of a task may not always be equal to its worst-case memory access demand in isolation. Analysis of the variable memory access demand of tasks due to cache persistence leads to significantly tighter worst-case response time (WCRT) of tasks.In this work, we show how the notion of cache persistence can be extended from single-core to multicore systems. In particular, we focus on analyzing the impact of cache persistence on the memory bus contention suffered by tasks executing on a multi-core platform considering both work conserving and non-work conserving bus arbitration policies. Experimental evaluation shows that cache persistence-aware analyses of bus arbitration policies increase the number of task sets deemed schedulable by up to 70 percentage points in comparison to their respective counterparts that do not account for cache persistence.pt_PT
dc.description.versioninfo:eu-repo/semantics/publishedVersionpt_PT
dc.identifier.doi10.23919/DATE48585.2020.9116265pt_PT
dc.identifier.issn1558-1101
dc.identifier.urihttp://hdl.handle.net/10400.22/16346
dc.language.isoengpt_PT
dc.peerreviewedyespt_PT
dc.publisherIEEEpt_PT
dc.relationPReFECT, ref. POCI-01-0145-FEDER-029119pt_PT
dc.relation.publisherversionhttps://ieeexplore.ieee.org/document/9116265pt_PT
dc.subjectCache storagept_PT
dc.subjectMultiprocessing systemspt_PT
dc.subjectProcessor schedulingpt_PT
dc.subjectReal-time systemspt_PT
dc.titleCache Persistence-Aware Memory Bus Contention Analysis for Multicore Systemspt_PT
dc.typeconference object
dspace.entity.typePublication
oaire.citation.conferencePlaceOnlinept_PT
oaire.citation.endPage447pt_PT
oaire.citation.startPage442pt_PT
oaire.citation.titleProceedings of the Design, Automation and Test in Europe Conference (DATE 2020)pt_PT
person.familyNameNelissen
person.familyNameTovar
person.givenNameGeoffrey
person.givenNameEduardo
person.identifier.ciencia-idE51E-C723-0D77
person.identifier.ciencia-id6017-8881-11E8
person.identifier.orcid0000-0003-4141-6718
person.identifier.orcid0000-0001-8979-3876
person.identifier.scopus-author-id41561808600
person.identifier.scopus-author-id7006312557
rcaap.rightsclosedAccesspt_PT
rcaap.typeconferenceObjectpt_PT
relation.isAuthorOfPublicatione23673cc-6b82-4d9c-94fb-4b4fca051b0d
relation.isAuthorOfPublication80b63d8a-2e6d-484e-af3c-55849d0cb65e
relation.isAuthorOfPublication.latestForDiscovery80b63d8a-2e6d-484e-af3c-55849d0cb65e

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