Alves, Gustavo R.Ferreira, José M.2014-04-242014-04-2419990-7803-5471-0http://hdl.handle.net/10400.22/4320A good verification strategy should bring near the simulation and real functioning environments. In this paper we describe a system-level co-verification strategy that uses a common flow for functional simulation, timing simulation and functional debug. This last step requires using a BST infrastructure, now widely available on commercial devices, specially on FPGAs with medium/large pin-counts.engconference object10.1109/ISCAS.1999.77779910.1109/ISCAS.1999.777799