Reis, CecíliaTenreiro Machado, J. A.2019-04-022019-04-022003-07-03http://hdl.handle.net/10400.22/13322This paper proposes a genetic algorithm for designing combinational logic circuits and studies three different case examples: the one-bit full adder, the four-bit parity checker and the two-bit multiplier. The objective of this work is to generate a functional circuit with the minimum number of gates.engCircuit designCombinational circuitsGenetic algorithmsComputer-aided designconference object