Awan, AliBletsas, KonstantinosSouto, PedroÅkesson, BennyTovar, EduardoAli, Jibran2017-02-062017-02-062016http://hdl.handle.net/10400.22/9515Work in Progress Session, 28th Euromicro Conference on Real-Time Systems (ECRTS 2016). 5 to 8, Jul, 2016. Toulouse, France.The state-of-the-art models and schedulability analysis for mixed-criticality multicore systems overlook low-level aspects of the system. To improve their credibility, we therefore incorprate, in this work, the effects of delays from memory contention on a shared bus. Specifically, to that end, we adopt the predictable memory reservation mechanism proposed by the Single Core Equivalence framework. Additionally, we explore how the reclamation, for higher-criticality tasks, of cache resources allocated to lower-criticality tasks, whenever there is a criticality (mode) change in the system, can improve schedulability.engSchedulabilityMixed-criticality multicore systemsconference object10.1109/RTCSA.2018.00022