Fidalgo, André VazAlves, Gustavo R.Ferreira, José M.2017-02-092017-02-092006-02http://hdl.handle.net/10400.22/9535II Jornadas sobre Sistemas Reconfiguráveis (REC’06)This paper proposes a set of modifications to the on-chip debugging infrastructures present in many actual microprocessor cores, with the objective of supporting the validation and verification steps of fault-tolerant mechanisms through fault injection campaigns. A synthesisable microprocessor core for programmable components was used as a target system an. a debugging infrastructure compliant with the NEXUS 5001 proposed standard for on- chip debugging was implemented on this target. To improve the process of real-time memory fault injection, an upgraded infrastructure designated as On-Chip Debugging and Fault Injection (OCD-FI) was developed. The complete system was analysed in terms of area overhead and fault injection capabilities and performance. All elements were designed as synthesizable VHDL modules and evaluated in simulation.engBoundary scanNEXUSFault injectionDependabilityconference object