Alves, Gustavo R.Amaral, TelmoFerreira, José M.2017-03-292017-03-291999http://hdl.handle.net/10400.22/9733A good verification strategy should bring near the simulation and real functioning environments. In this paper we describe a system-level co-verification strategy that uses a common flow for functional simulation, timing simulation and functional debug. This last step requires using a BST infrastructure, now widely available on commercial devices, specially on FPGAs with medium/large pin-counts.engFPGAsBoundary Scan Testconference object