Alves, Gustavo R.Gericota, Manuel G.Ramalho, José L.Ferreira, José M.2017-01-091993-090-8186-4350-1http://hdl.handle.net/10400.22/9160Boundary scan is now the most promising technology for testing high-complexity printed circuit boards. The number of BST components available to board-level designers is however still restricted, limiting the achievable fault coverage. The requirements to improve board-level testability are analysed, and a corresponding set of testability building blocks are proposed. A low-cost and maximum-flexibility solution is described, which implements these blocks on medium-complexity PLDs, using a simple and powerful HDL.engDesign for testabilityBoundary scanjournal article10.1109/EURDAC.1993.410669