Utilize este identificador para referenciar este registo: http://hdl.handle.net/10400.22/7209
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dc.contributor.authorBarros, António-
dc.contributor.authorPinho, Luís Miguel-
dc.contributor.authorMeumeu Yomsi, Patrick-
dc.date.accessioned2015-12-21T17:07:44Z-
dc.date.available2015-12-21T17:07:44Z-
dc.date.issued2015-
dc.identifier.urihttp://hdl.handle.net/10400.22/7209-
dc.description.abstractRecent embedded processor architectures containing multiple heterogeneous cores and non-coherent caches renewed attention to the use of Software Transactional Memory (STM) as a building block for developing parallel applications. STM promises to ease concurrent and parallel software development, but relies on the possibility of abort conflicting transactions to maintain data consistency, which in turns affects the execution time of tasks carrying transactions. Because of this fact the timing behaviour of the task set may not be predictable, thus it is crucial to limit the execution time overheads resulting from aborts. In this paper we formalise a FIFO-based algorithm to order the sequence of commits of concurrent transactions. Then, we propose and evaluate two non-preemptive and one SRP-based fully-preemptive scheduling strategies, in order to avoid transaction starvation.pt_PT
dc.language.isoengpt_PT
dc.publisherElsevierpt_PT
dc.relationFCOMP-01–0124-FEDER-015006 (VIPCORE)pt_PT
dc.relationFCOMP-01–0124-FEDER-037281 (CISTER)pt_PT
dc.relationARTEMIS/0003/2012, JU grant nr. 333053 (CONCERTO)pt_PT
dc.relation.ispartofseriesJournal of Systems Architecture;Vol. 61, Issue 10-
dc.rightsclosedAccesspt_PT
dc.subjectReal-time systemspt_PT
dc.subjectSynchronization mechanismspt_PT
dc.subjectSoftware Transactional Memorypt_PT
dc.subjectNon-preemptive schedulingpt_PT
dc.subjectStack Resource Protocolpt_PT
dc.subjectCache non-coherencypt_PT
dc.subjectMulti-core platformspt_PT
dc.subjectContention managementpt_PT
dc.titleNon-preemptive and SRP-based fullypreemptive scheduling of real-time Software Transactional Memorypt_PT
dc.typearticlept_PT
dc.peerreviewedyespt_PT
degois.publication.firstPage553pt_PT
degois.publication.issue10pt_PT
degois.publication.lastPage566pt_PT
degois.publication.titleJournal of Systems Architecturept_PT
degois.publication.volume61pt_PT
dc.relation.publisherversionhttp://www.sciencedirect.com/science/article/pii/S1383762115000788pt_PT
dc.identifier.doihttp://dx.doi.org/10.1016/j.sysarc.2015.07.008pt_PT
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