Utilize este identificador para referenciar este registo: http://hdl.handle.net/10400.22/6713
Título: TEA: Timing and Energy Aware compression architecture for Efficient Configuration in CGRAs
Autor: Jafri, Syed M.A.H.
Daneshtalab, Masoud
Hemani, Ahmed
Awan, Muhammad Ali
Plosila, Juha
Palavras-chave: Reconfigurable architectures
CGRA configuration
Coarse grained reconfigurable architectures
Compression/decompression hierarchy
Adaptive systems
Data: 23-Mai-2015
Editora: Elsevier
Relatório da Série N.º: Microprocessors and Microsystems;
Resumo: Coarse Grained Reconfigurable Architectures (CGRAs) are emerging as enabling platforms to meet the high performance demanded by modern applications (e.g. 4G, CDMA, etc.). Recently proposed CGRAs offer time-multiplexing and dynamic applications parallelism to enhance device utilization and reduce energy consumption at the cost of additional memory (up to 50% area of the overall platform). To reduce the memory overheads, novel CGRAs employ either statistical compression, intermediate compact representation, or multicasting. Each compaction technique has different properties (i.e. compression ratio, decompression time and decompression energy) and is best suited for a particular class of applications. However, existing research only deals with these methods separately. Moreover, they only analyze the compaction ratio and do not evaluate the associated energy overheads. To tackle these issues, we propose a polymorphic compression architecture that interleaves these techniques in a unique platform. The proposed architecture allows each application to take advantage of a separate compression/decompression hierarchy (consisting of various types and implementations of hardware/software decoders) tailored to its needs. Simulation results, using different applications (FFT, Matrix multiplication, and WLAN), reveal that the choice of compression hierarchy has a significant impact on compression ratio (up to 52%), decompression energy (up to 4 orders of magnitude), and configuration time (from 33 n to 1.5 s) for the tested applications. Synthesis results reveal that introducing adaptivity incurs negligible additional overheads (1%) compared to the overall platform area.
Peer review: yes
URI: http://hdl.handle.net/10400.22/6713
DOI: 10.1016/j.micpro.2015.05.002
Versão do Editor: http://www.sciencedirect.com/science/article/pii/S014193311500054X
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